Phase-lock loop (PLL) circuits have generally been provided in order to provide a fixed frequency clock signal that is provided to a core of an integrated circuit, for example. That is, a PLL may synthesize a high frequency core clock signal from a low reference clock signal. The PLL may be powered from an analog power supply (VCCA) or from a filtered power supply in order to ensure a constant clock frequency even in the event of voltage droops. Voltage droop may occur when a level of activity changes, such as changes from a high activity level to a low activity level or from a low activity level to a high activity level. The change of activity level may cause a current surge to occur, which may in turn, cause the voltage to droop. These voltage droops may be factored into component design such that the components operate during voltage droops. As voltages scale down and droop percentages increase, additional timing margins may be required to be able to function at the target frequencies, such as the target frequency of the core.